1. Field of the Invention
Embodiments of the present invention are related to memory devices. In particular, embodiments of the invention are related to a flash memory device in which the total programming time may be reduced. Embodiments of the invention are also related to programming methods for such a flash memory device.
This application claims priority to Korean Patent Application No. 2005-50470, filed Jun. 13, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
An increasing need exists for non-volatile semiconductor memory devices that may be programmed and erased without the requirement of providing a data refresh operation for data stored in the device. The general trend in all semiconductor memory device development is one characterized by increased storage capacity and a high degree of integration. The NAND flash memory device is one example of a non-volatile semiconductor memory device that provides large storage capacity and a high degree of integration. Since the NAND flash memory device retains stored data even when power is not supplied to the device, it is used widely in electronic devices, such as portable terminals, portable computers, and the like, which can suffer sudden power interruptions.
Conventional NAND flash memory devices typically comprise electrically erasable and programmable read-only memory cells called “flash EEPROM cells.” In general, a flash EEPROM cell comprises a cell transistor formed from a semiconductor substrate (or bulk) of first conductivity type (e.g., P-type), and source and drain regions of second conductivity type (e.g., N-type). The source and drain regions are separated by a channel region, and a floating gate is formed on the channel region. The floating gate stores electrons and controls the gate function for the cell transistor.
One conventional memory cell array comprising flash EEPROM cells (hereinafter, referred to as memory cells) having the structure described above is illustrated in FIG. 1. Of note, in the preceding description, when a layer or element is referred to as being formed “on” another element or layer, it may be formed directly on that layer, or intervening layers may be present.
Referring to FIG. 1, a memory cell array (or memory block) 1 comprises a plurality of cell strings (or NAND strings) 10 corresponding to bit lines BL0 through BLn−1, respectively. Each cell string 10 comprises a string select transistor SST as a first select transistor, a ground select transistor GST as a second select transistor, and a plurality of memory cells M(x)0 through M(x)(m−1) (where x is a number between 0 and (n−1)). String select transistor SST has a drain connected to a corresponding bit line and a gate connected to a string select line SSL. Ground select transistor GST has a source connected to a common source line CSL and a gate connected to a ground select line GSL. Memory cells M(x)0 through M(x)(m−1) are connected in series between a source of string select transistor SST and a drain of ground select transistor GST. Memory cells M(x)0 through M(x)(m−1) are connected to corresponding word lines WL0 through WLm−1, respectively. Word lines WL0 through WLm−1, string select line SSL, and ground select line GSL are driven by a row selector circuit (not shown).
In order to program the memory cells of a selected row (or word line) of a NAND flash memory device, the memory cells in a memory block (or a memory cell array) are first erased in order to give each memory cell a threshold voltage that is below 0V. Once the memory cells are erased, program data is loaded onto a page buffer circuit of the NAND flash memory device, and then a high voltage pump circuit generates relatively high voltages for a programming operation (e.g., a pass voltage and a program voltage are supplied to word lines). Afterward, the loaded data is programmed into the memory cells of a selected word line by the iteration of program loops. Each of the program loops consists of a bit line setup interval, a program interval, a discharge/recovery interval, and a verification interval.
During the bit line setup interval, bit lines BL0 through BL(n−1) are charged to a power supply voltage or a ground voltage in accordance with the loaded program data. That is, a bit line connected to a memory cell to be programmed is charged to the ground voltage, and a bit line connected to a memory cell to be program inhibited (i.e., not programmed) is charged to the power supply voltage. Within the program interval, the program voltage is supplied to a selected word line and the pass voltage is supplied to the unselected word lines. For memory cells connected to bit lines that are charged to the ground voltage, a bias condition great enough to induce F-N tunneling is satisfied, so electrons are injected to the floating gates of the memory cells from the bulk. On the other hand, as is well known in the art, memory cells connected to bit lines that are charged to the power supply voltage are program inhibited. The voltages of the bit lines and the word lines are discharged during the discharge interval, which functions as a recovery interval, and whether memory cells have a target threshold voltage is determined during the verification interval.
The programming operation described above is disclosed in U.S. Pat. No. 6,353,555, the subject matter of which is hereby incorporated by reference in its entirety. A program inhibition method is disclosed in U.S. Pat. Nos. 5,677,873, and 5,991,202, and the subject matter each of these patents is hereby incorporated by reference in its entirety.
In accordance with the above description, the program voltage is supplied to a selected word line during a program interval (i.e., a program execution time). Application of the program voltage to a selected word line is made during the program interval, which accounts for a large portion of a program loop time (i.e., the length of time needed to execute a program loop). In general, the length of the program interval is determined in accordance with RC delay time and the program voltage restoration time, each of which will be described below.
For each memory cell of a selected word line, the time needed to set the control gate voltage of the memory cell to the program voltage varies in accordance with the distance of the memory cell from the row selector circuit of the NAND flash memory device. That is, referring to FIG.1, the time needed to set the control gate voltage of a cell A, which is relatively near the row selector circuit, is shorter than the time needed to set the control gate voltage of a cell B, which is relatively far from the row selector circuit, because the control gate loading and corresponding signal flight time for cell B is greater than that of cell A. That is, different RC delay periods exist between memory cells A and B which are connected to the same word line.
When a program voltage is supplied to a selected word line, the voltage supplied drops below a target voltage due to the process of loading the selected word line. A high voltage generator circuit restores the supplied program voltage to the target voltage. The time needed to restore the reduced program voltage to the target voltage is called the program voltage restoration/recovery time.
Unfortunately, both the program voltage restoration time and the RC delay time vary in accordance with process, voltage, and peripheral conditions. For this reason, these times are set in order to accommodate for the worst case conditions (i.e., the conditions that would cause the program voltage restoration time and the RC delay time to be the longest). That is, a margin is added to the program execution time in order to accommodate for the worst case conditions.
In order to meet the continuous need for high-speed memories, it would be beneficial to reduce the program loop time (i.e., a total programming time).